1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having an embedded chip and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To meet the miniaturization requirement of semiconductor packages, wafer level packaging (WLP) technologies have been developed.
U.S. Pat. Nos. 6,452,265 and 7,202,107 provide fabrication methods of wafer-level packages. FIGS. 1A to 1E are cross-sectional views showing a fabrication method of a semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a thermal adhesive layer 11 is formed on a carrier 10.
Referring to FIG. 1B, a plurality of chips 12 are disposed on the thermal adhesive layer 11. Each of the chips 12 has an active surface 12a with a plurality of electrode pads 120 and an inactive surface 12b opposite to the active surface 12a, and the chips 12 are disposed on the thermal adhesive layer 11 via the active surfaces 12a thereof.
Referring to FIG. 1C, an encapsulant 13 is formed on the chips 12 and the thermal adhesive layer 11.
Referring to FIG. 1D, the thermal adhesive layer 11 and the carrier 10 are removed to expose the active surfaces 12a of the chips 12.
Referring to FIG. 1E, a circuit structure 14 is formed on the encapsulant 13 and the active surfaces 12a of the chips 12 and electrically connected to the electrode pads 120 of the chips 12.
However, when the chips 12 are disposed on the plate-shaped carrier 10 having the thermal adhesive layer 11, it is difficult to align the chips 12 on the carrier, thus easily causing displacement of the chips 12 and reducing the product reliability.
In addition, since the thermal adhesive layer 11 is adhesive, it may expand or contract due to its coefficient of thermal expansion (CTE) during the fabrication process, such that displacement of the chips 12 tends to occur. For example, during formation of the encapsulant 13, the thermal adhesive layer 11 is softened by heat to cause displacement of the chips 12. Consequently, the circuit structure 14 to be formed later cannot be precisely connected to the electrode pads 120 of the chips 12, thereby resulting in poor electrical performance and product reliability.
Therefore, how to overcome the above-described drawbacks has become critical.